Digital Logic

Course Title: Digital Logic (3 Cr.)
Course Code: CACS105
 Class Load: 5 Hrs./ Week (Theory: 3 Hrs. Practical: 2 Hrs.)

 Unit I Introduction 

             1.1 Digital Signals and Wave Forms 

             1.2 Digital Logic and Operation 

             1.3 Digital Commser mid Integrated Circuit, (IC) 

             1.4 Clock Wave Form 

Unit 2 Number Systems

            2.1 Binary, Octal. & Hexadecimal Number Systems and 'Their                            Conversions
                     2.1.1 Representation of Signed Numbers-Floating Point Number
                     2.1.2 Binary Arithmetic
             2.2 Representation-of BCD-ASCII-Excess 3 -Gray Code -Error Detecting                             and Correcting Codes
. 

Unit 3 Combinational Logic Design

             3.1 Basic Logic Gates NOT, OR and AND
             3.2 Universal Logic Gates NOR and NAND
             3.3 EX-OR and EX-NOR Gates
             3.4 Boolean Algebra
                  3.4.1 Postulates .& Theorems
                  3.4.2 Canonical Forms Simplification of Logic Functions
            3.5 Simplification of Logic function using K-Map
                 3.5.1 Analysis of SOP and POS Expression
           3.6 Implementation of Combinational Logic Functions
                 3.6.1 Encoders & Decodes 

                 3.6.2 half Adder. & Full Adder
           3.7 Implementation of Data Processing Circuits
                 3.7.1 Multiplexers and De-Multiplexers
                 3.7.2 Parallel Adder -Binary Adder-Parity Generator /                              Checker-Implementation of Logical Functions Using Multiplexers.
         3.8 Basic Concepts of Programmable Logic
                    3.8.1 PROM
                    3.8.2 EPROM
                    3.8.3 PAL
                    3.8.4 PLA 

Unit 4 Counters & Registers
            4.1 RS. JK, JK Master - Slave. I) & T Flip flops
                   4.1.1 1 evel Triggering and Edge Triggering
                   4.1.2 Excitation Tables
           4.2 Asynchronous and Synchronous Counters
                   4.2.1 Ripple Counter Circuit and State Diagram and Timing                            Waveforms
                   4.2.2 Ring Counter: Circuit and State Diagram and Timing                              Wavefomts
                   4.2.3 Modulus 10 Counter. Circuit and State Diagram and Timing                        Waveforms
                   4.2.4 Modulus Counters (5, 7. II) and Design Principle, Circuit and                      State Diagram
                   4.2.5 Synchronous Design of Above Counters. Circuit Diagrams and                State Diagrams
           4.3 Application &Counters
                   4.3.1 Digital Watch
                   4.3.2 Frequency Counter
           4.4 Registers
                    4.4.1 Serial in Parallel out Register
                    4.4.2 Serial in Serial out Register
                    4.4.3 Parallel in Serial out Register
                   4.4.4 Parallel in Parallel out Register
                   4.4.5 Right Shift.,Left Shill Register 

Unit 5 Sequential Logic Design
            5.1 Basic Models of Sequential Machines
                    • Concept of State
                   • State Diagram
           5.2 State Reduction through Partitioning and Implementation of                              Synchronous Sequencial Circuit
           5.3 Use of Flip-Flops in Realizing the Models
           5.4 Counter Design